AMD demonstrates the most powerful AI accelerator MI455X: TSMC 2nm process, 320 billion transistors, 432GB HBM4

IT House reported on July 24 that today (July 24) at Advancing AI 2026, the annual event held in San Francisco, USA, AMD Chairman and CEO Su Zifeng delivered a keynote speech and announced more details of the next-generation AI accelerator Instinct MI455X. In terms of process, the Instinct MI455X GPU has 320 billion transistors and is built using advanced packaging technology. Its design consists of four accelerator composite core dies (XCD) stacked on fabric and cache core dies (FCD) through hybrid bonding. Both FCDs are packaged using TSMC’s CoWoS-L technology and connected to 6 HBM4 stacks and 2 I/O Dies. IT Home has attached relevant pictures as follows: The new Helios rack-level architecture integrates the video memory of 72 MI455X GPUs into a unified coherent domain for the first time. This is a key step for AMD to benchmark Nvidia NVL72. Combining the improved tensor data handling unit and new multicast read support in CDNA 5, AMD is focused on improving chip data movement efficiency. Su Zifeng said that through this chiplet design, AMD uses TSMC's most advanced 2N GAA (gate around) on the XCD to most effectively improve power consumption and performance; while the FCD and I/O Die parts are manufactured using TSMC's N3P process. In terms of CDNA 5 architecture, AMD now calls the basic building unit of the CDNA 5 accelerator complex chip (Accelerator Complex Die) "Work Group Processor" and no longer calls it "Compute Unit". The number of WGPs of MI455X is the same as that of the previous generation MI355