AMD releases sixth-generation EPYC Venice CPU: TSMC 2nm process, 256 cores, 203 billion transistors, 5GHz+ frequency

IT House reported on July 24 that today (July 24) at Advancing AI 2026, the annual event held in San Francisco, USA, Su Zifeng, Chairman and CEO of AMD, delivered a keynote speech and introduced AMD’s sixth-generation EPYC Venice CPU. In terms of technology, this flagship server CPU is the first to be mass-produced using TSMC’s 2nm process and integrates 203 billion transistors. The compute chiplet uses a 2nm process, while the I/O Die part uses a 6nm process. IT Home Note: The biggest highlight of TSMC’s 2nm process is the transition from FinFET to GAA (nanosheet transistor). The performance is improved by 10-15% under the same power consumption, the power consumption is reduced by 25-30% under the same performance, and the transistor density can be increased by up to 15%. The first of these flagship processors is the EPYC 9006 "SP7" server CPU, which features 256 "Zen 6" cores, 512 threads, up to 1.6 TB/s bandwidth, and support for PCIe Gen6 at up to 64 Gbps AIC speeds. The chip is designed to achieve extremely high frequencies of up to 5.0 GHz with 96 working cores. The second SP8 Venice "EPYC 9006" chip is designed for mainstream servers with 8 to 128 core configurations. The chip will support 8-channel DDR5, support 2 DIMMs per channel, provide 128 PCIe Gen 6.0 lanes, and be flexible to deploy in 1P and 2P solutions. Compared with its previous generation EPYC Turin series, the new products also show significant generational improvements. EPYC Venice’s agent processing power per watt is 1.7 times that of the previous generation, performance per watt is improved by 1.4 times, and the number of tokens processed per second (tok