Target turnaround time halved: Rapidus and Cadence jointly promote AI assistance in chip design

IT House reported on July 20 that Japanese advanced semiconductor manufacturer Rapidus and chip EDA & IP giant Cadence announced last week a cooperation in the field of AI assistance in chip design to promote the application of AI agents in advanced process SoC design, with the goal of halving the turnaround time (TAT) of chip design. IT House has learned that Rapidus has added two tools, Raads Navigator and Raads Indicator, to its AI-assisted design solution product line Raads to integrate with Cadence's InnoStack AI Super Agent, enabling intelligent agent design orchestration in key SoC workflows and automatically coordinating tasks from early architecture exploration to implementation and final acceptance. This integration is designed to help teams manage the complexity of advanced nodes, increase design predictability, and improve engineering efficiency by applying data-driven optimization throughout the design lifecycle, while supporting Rapidus' goal of reducing design turnaround times.